The present invention relates to a semiconductor memory device, particularly to a static RAM using memory cells based on flip-flops.
Recently higher-density static RAMs are increasingly demanded, and it is required to further diminish the memory cells.
A static RAM of FIGS. 15, and 16A to 16C has been proposed. FIG. 15 shows the general fabrication of the proposed static RAM, and FIGS. 16A to 16C show the constitution of the respective memory cells. FIG. 15 is a general plan view of the memory cell, FIG. 16A is a plan view of the respective memory cells, FIG. 16B is a sectional view of the respective memory cells along the line D-D', and FIG. 16C is the circuit diagram of the respective memory cells.
As shown in FIGS. 16A to 16C, each memory cell has a pair of device regions 104, 105 defined by a field oxide film 102 on a p-semiconductor substrate 100. A driver transistor D1 and a transfer transistor T1 are formed in the one device region 104, and a driver transistor D2 and a transfer transistor T2 are formed in the other device region 105.
In the device region 104 a gate layer 108 for the driver transistor D1 is formed through a gate oxide film 106, and a gate layer 109 for the driver transistor D2 is formed through a gate oxide film 106 in the device region 105. The gate layer 108 crosses the drive region 104 forming the driver transistor D1 and arrives at the other device region 105 to be in contact with an n-doped region 110. Similarly the gate layer 109 crosses the device region 105 forming the driver transistor D2 and arrives at the device region 104 to be in contact with an n-doped region 110.
A Vss contact 112 which is connected to a source wire (not shown) is formed in the n-doped region 110 adjacent to a channel region of the driver transistor D1 of the device region 104. Similarly a Vss contact 113 which is connected to a source wire (not shown) is formed in the n-doped region 110 adjacent to a channel region of the driver transistor D2 in the device region 105.
In the device region 104 a word line 114 is formed across the device region 104 through the gate oxide film 106 and functions also as a gate layer of the transfer transistor T1. In the device region 105 a word line 115 is formed across the device region 105 through the gate oxide film 106 and functions also as a gate layer of the transfer transistor T2.
A word line WL of aluminium is formed on the top layers of the word lines 114, 115. Each word line WL is in contact with the word lines 114, 115 of a set number of memory cells so that the word lines 114, 115 are less resistivity.
A bit line contact 116 which is in contact with a bit line BL is formed in the n-doped region 110 adjacent to the channel region of the transfer transistor T1 of the device region 104. Similarly a bit line contact 117 which is in contact with a bit line BL is formed in the n-doped region 110 adjacent to the channel region of the transfer transistor T2.
A TFT (Thin Film Transistor) load device (not shown) is provided above the driver transistors D1, D2 of each memory cell.
As shown in FIG. 15, a number of memory cells of FIGS. 16A to 16C are arranged in a matrix. A pair of word lines 114, 115 are formed over adjacent ones of the memory cells.
But in the above-described static RAM the word lines 114, 115 function as the gate layers of the transfer transistors T1, T2 and are formed of the same polycrystalline silicon layer as the gate layers 108, 109 of the driver transistors D1, D2. This has made it difficult to reduce the memory cell area.
As shown in FIG. 16A, gaps (G1) of, e.g., about 0.5 .mu.m are necessary between ends of the gate layers 108, 109, and edges of the word lines 114, 115 for patterning of the polycrystalline silicon layer.
The gate layers 108, 109 require about 0.5 .mu.m-projections (G2) at ends thereof in consideration of allowances for aligning masks for patterns for forming the gate layers 108, 109 and the device regions 104, 105.
To these ends it is necessary to design the word lines 114, 115 and the device regions 104, 105 so as to be spaced from each other by an about 1.0 .mu.m distance (=Gi+G2).
Thus the above-described static RAM requires the useless region for the mask alignment, which results in a problem that each memory cell needs a large area. Reduction of an area of each memory cell results in a problem that the driver transistors D1, D2 have small channel widths and have insufficient drive ability.
Furthermore, in the above-described static RAM each memory cell requires two word lines, which needs a larger area.